`timescale 1ns/1ps

module adder_tb;

	parameter WIDTH = 3;
	
	reg [WIDTH - 1 : 0] in_0;
	reg [WIDTH - 1 : 0] in_1;

	wire [WIDTH - 1 : 0] out;

	initial begin
		#0 in_0 <= 0;
		#0 in_1 <= 0;
	 	#10 in_1 <= 1;
	 	#10 in_0 <= 2;
	 	#10 in_1 <= 3;
	 	#10 in_0 <= 4;
	 	#20 $stop;
	end

	adder a1 (in_0, in_1, out);

	// 打印
	initial begin
		$monitor("At time %t, in_0 = %0d, in_1 = %0d, out = %0d", $time, in_0, in_1, out);
		if (in_0 + in_1 != out) begin
			$monitor("error!");
			$stop;
		end
	end

	// 产生波形
	initial begin
		$dumpfile("adder.vcd");
		$dumpvars(0, a1);
	end

endmodule